The invention relates to a method for the simulation of an electrical circuit, which can be described by a layout.
The behavior of integrated electrical circuits is often influenced by parasitic effects that are caused by lines.
Undesired capacitive effects are of particular importance in this context that are caused by electrical conductors which run in direct proximity or are arranged next to one another. Electrical conductors can be described by capacitances and by nonreactive resistances. Such capacitive effects caused by conductors are therefore also referred to as parasitic capacitances.
Parasitic capacitances cannot be disregarded in various analyses of integrated electrical circuits, for example when determining the delay or crosstalk. Electrical circuits of great complexity can become unusable due to undesired effects caused by such parasitic capacitances. On account of the large dimension of the network listxe2x80x94generated by an extractionxe2x80x94with parasitic elements, taking account of parasitic capacitances in the simulation of electrical circuits leads to performance problems both in the extraction and in the subsequent analysis steps.
The extraction is often performed in a planar manner. Although the resulting network list comprises all the relevant information, the performance of the extraction and of the subsequent analysis steps on the basis of such a network list proves to be unsatisfactory on account of the very large volumes of data to be handled.
One alternative to this is a hierarchical procedure, in which all the instances of a given cell are entered identically into the network list. It is thereby disadvantageous that the different environments of cell entities are not taken into account and, as a result, an accurate simulation of the electrical circuit is not possible.
A further possibility consists in outputting each entity of a cell as a dedicated variant. With this procedure, it is disadvantageous that the resulting network list contains a very large number of cells and is correspondingly unwieldy in its further processing. Performance problems arise here as well.
A solution approach according to which cells are classified in accordance with their environment is not known in the prior art.
It is accordingly an object of the invention to provide a method of simulating an electrical circuit that can be described by its layout, and to provide corresponding computer is software as well as nd data carriers, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables an advantageous simulation of electrical circuits, and takes into account effects caused by parasitic capacitances.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of simulating an electrical circuit that can be described by a layout with a multiplicity of cells. The layout has the following features:
the cells have one or more networks described by geometrical data and subdivided into one or more models of electrical circuit elements;
the cells have information about those layers on which the networks are present; and
the cells have references to further cells.
The method comprises the following steps:
a) extracting node information from a layout;
b) determining and recording coupling capacitance values of the networks with isolated consideration of the cells;
c) determining and recording environment-dependent coupling capacitance values of the networks for all of the cell entities;
d) determining and recording intrinsic capacitance values of the networks for each cell;
e) determining and recording intrinsic capacitance values of the networks for all of the cell entities;
f) calculating a respective comparison capacitance value for each network with isolated consideration of the cells;
g) calculating differential capacitance values of each network with respect to a respective comparison capacitance value for all of the cell entities;
h) classifying the cell entities of each cell into different variants for all of the networks by using the differential capacitance values as a basis; and
i) simulating a behavior of the electrical circuit using the variants of the cell entities determined in the preceding step.
In accordance with an added feature of the invention, the above step h) is replaced with the following:
h1) defining a tolerance value T and a value for an index k;
h2) selecting a cell from the layout;
h3) selecting a network of the cell selected in step h2);
h4) selecting a k-th cell entity of the cell;
h5) determining the differential capacitance value Dk for the k-th cell entity from a difference in a sum of the intrinsic and lateral capacitance values for the network selected in step h3) and from a sum of the intrinsic and lateral capacitance values of the network in the k-th cell entity;
h6) testing whether a variant V exists for which |Dkxe2x88x92Dv|xe2x89xa6T and, if the variant V exists, continuing with step h8), otherwise continuing with step h7);
h7) forming a new variant V with Dv=Dk;
h8) classifying the k-th cell entity of the cell into the variant V;
h9) incrementing the index k;
h10) testing whether a k-th cell entity of the cell exists and, if a k-th entity exists, continuing with step h4), otherwise:
h11) testing whether a further network exists in the cell under consideration, if the further network exists, selecting the network, defining a value for the index k, and continuing with step h4).
In this case, the intention is to utilize the hierarchy existing in the layout and to take account of the different environments of various entities of identical cells in the resulting network list.
According to the invention, an electrical circuit can be described by a layout and, after the extraction, by a network list.
The layout contains a geometrical description of all the circuit elements arranged on the electrical circuit. This geometrical description is designed in particular in the form of polygons or rectangles.
In accordance with another feature of the invention, steps h2) to h11) are repeated for further cells of the network list.
In accordance with an additional feature of the invention, the above steps h6), h7), and h8) are replaced with the following, starting with a second network under consideration,
h6xe2x80x2) testing whether a variant V exists for which |Dkxe2x88x92Dv|xe2x89xa6T and, if the variant does not exist, continuing with step h7xe2x80x2);
h6xe2x80x3) testing whether the k-th cell entity and the cell entities already contained in the variant V have previously been classified in different variants V and, if not, continuing with step h8xe2x80x2);
h7xe2x80x2) forming a new variant V with Dv=Dk; and
h8xe2x80x2) classifying the k-th cell entity of the cell into the variant V.
In accordance with a further feature of the invention, coupling capacitances and intrinsic capacitances are extracted in one step as opposed to extracting separately.
In a preferred embodiment of the invention, there are extracted only coupling capacitances or only intrinsic capacitances.
In this case, the layout is subdivided into a multiplicity of cells which each have one or more networks, which are described by geometrical data and contain one or more models of electrical circuit elements. By way of example, a simple cell may contain all those polygons which together represent an inverter. Furthermore, the cells contain information about those layers of the electrical circuit on which the networks or the circuit elements are present. In this case, each polygon is assigned that layer on which the corresponding network or the corresponding electrical circuit element is modeled on the electrical circuit. Furthermore, many cells have references to further cells. In this case, it is possible to insert or instantiate cells into other cells. By way of example, one cell can be inserted as often as desired into other cells. The networks of instantiated cells are identical in all instantiations but often have different environments. This affects the parasitic elements of the networks of the cell, in particular the parasitic capacitances.
Network is the term used to denote the conductive connection between different structural parts, for example between a transistor output and a transistor input. The connections of a capacitance are present as precisely two networks. Electrical information can be transmitted from one network to a further network via a capacitance. Therefore, it is also the that a capacitance connects two networks.
Capacitances can be subdivided into lateral and intrinsic capacitances. The connection to such capacitances constitutes a property of the respective network. In more general form, lateral capacitances can also be designated as coupling capacitances. Coupling capacitances exist between two signal networks, while the intrinsic capacitance exists between a signal network and ground. The method according to the invention can be used for any desired couplings.
In the geometrical sense, i.e. in the layout, the set of all polygons whose processing in the fabrication of an integrated circuit forms a conductive connection between two structural parts corresponds to a network. The polygons belonging to a network are always at the same electrical potentialxe2x80x94disregarding propagation time delays of electrical signals. A network can generally be found in the layout only after an extraction, since polygons of different layers can contribute to the network.
According to the invention, a network list is also used for the simulation of an electrical circuit. By means of an extraction, an electrical description is created from the existing layout, the format of which description is designated as network list and the information content of which description corresponds to that of a circuit diagram.
Extraction is understood to be that method in which node information or network names are assigned to the polygons. This involves analysis of which of the polygons are conductively connected after the fabrication process. These polygons are assigned the same node, i.e. these polygons acquire the same network name.
Examples of known network list formats are SPICE or DSPF. If, during the extraction, not only the desired structural parts such as, for example, transistors are included in the network list, but the parasitic, undesirable properties of the lines are also described electrically, then the term xe2x80x9cparasitics extractionxe2x80x9d is employed. In this case, the lines are usually described by nonreactive resistances and by capacitances. The parasitics extraction generates a network list from an existing layout. The simulation of this network list then corresponds to the behavior of the electrical circuit produced in reality later.
The network list comprises information about the cells contained in it and about their electrical connections. Furthermore, the network list may in each case have one or more entities of cells. The capacitances present in the network list after the parasitics extraction can be subdivided into coupling capacitances with respect to other networks and into intrinsic capacitances with respect to ground. The network list no longer contains information about the polygons but rather only information about the electrical connections. Such a network list can be generated from the extracted layout.
The application of variant classification in accordance with the invention does not require a network list. A network list is generated at a later point in time, to be precise when the exact extraction of all the parasitic elements has been done on the basis of the variant classification of the method according to the invention. A network list containing said variants as cells is then generated. In this case, the network list can be generated by the use of suitable software, in particular the commercial software Assura from Cadence. The circuit simulation of the resulting hierarchical network list can be effected by using software, in particular the software product HSIM from Nassda Corporation.
The method according to the invention is not based on a network list but rather directly on an extracted layout. The extracted layout contains the geometrical information and also the information about the network association. The method is based on these two items of information. Basing the method according to the invention on a network list is conceivable when the network list already contains all of the information about cell- and entity-dependent capacitances.
Firstly, the capacitance values are determined and recorded for the couplings with an isolated consideration of the cells. The environment-dependent capacitance values of the couplings are then determined individually and recorded for all of the cell entities. The intrinsic capacitance values are subsequently determined and recorded separately for each cell. Afterward, the intrinsic capacitances of the networks are determined and recorded for all of the cell entities of the cells.
In the next method step, a respective comparison capacitance value is calculated for each network with isolated consideration of the cells. This comparison capacitance value results from the sum of the capacitance values of the coupling capacitances and intrinsic capacitances contained in the cell considered. Neither the environment of the cells considered nor possible xe2x80x9coverridesxe2x80x9d are taken into account in this case. xe2x80x9cOverridesxe2x80x9d are understood as polygons which act on networks in deeper cells and alter their geometry.
In a next method step, the differential capacitance values of each network with respect to the comparison capacitance value determined in the previous step are calculated for all of the cell entities. The environment-dependent coupling capacitance values and xe2x80x9coverridesxe2x80x9d present on other planes are taken into account in this case. The respective differential capacitance value in this case results from the difference in the capacitance value for the respective cell entity, which takes account of the environment-dependent capacitance values of the networks and/or the xe2x80x9coverridesxe2x80x9d present on other planes, and from the comparison capacitance value determined in the previous step.
In the next step, the cell entities of each cell are classified into different variants for all of the networks. This is based on the differential capacitance values determined in the previous step. Cell entities classified into identical variants in each case have similar environment-dependent, capacitive properties.
In the concluding method step according to the invention, the behavior of the electrical circuit is simulated using the variants thus determined, in which the cell entities are classified.
The extraction and the simulation of an electrical circuit are very time-consuming precisely in the case of complex circuits, particularly if each cell entity is extracted individually without accessing results that have already been determined and can be transmitted. Hierarchical network lists, which contain not only electrical circuit elements and their connecting lines but also calls or instantiations of further cells whose behavioral description is likewise present as a network list, are suitable for accelerating extractions and simulations. Such cells are extracted and simulated separately. The data, once calculated in the context of the extraction, can be accessed as often as desired without calculating them anew.
The parasitics extraction can be accelerated if multiply instantiated cells are extracted only once. In the parasitics extraction, however, the problem arises that each cell entity has its individual environment and, therefore, formally identical cell entities differ in their capacitive properties in an environment-dependent manner. In the case of the known procedure of parasitics extraction, all the cell entities of a cell are taken into account by a single definition in the network list. This leads, of course, to losses in the accuracy of the extraction and the simulation.
In order to ensure one hundred percent accuracy in the extraction and also in the simulation, every cell entity must be extracted in a manner dependent on its individual environment. This leads to unacceptable run times during the extraction and during the simulation. In this case, the volume of data corresponds to that of a planar extraction. A one-bit cell of a 256 MB DRAM chip leads to an output of 256 million cell entities in the corresponding network list. However, most of these cell entities are identical in their electrical and capacitive properties.
A basic concept of the invention consists in classifying all of the cell entities which occur in a network list into variants on the basis of their capacitive properties governed by their respectively different environment, the cell entities contained in the same variant in each case having similar capacitive properties and the number of variants being kept manageable. In this case, each cell variant covers the behavior of as many cell entities as possible. Geometrically, this corresponds to the assumption of identical environments of these cell entities.
The cell variants to be generated differ in their parasitic elements. In order to utilize the advantages of a hierarchical extraction and simulation, the number of different cell variants is kept manageable. According to the invention, the cell entities are already assigned to a respective variant before the actual performance of the parasitics extraction. This is referred to as xe2x80x9cupfront variant identificationxe2x80x9d. The method according to the invention furthermore solves the problem that the actual parasitics are still not known at all at this point in time, a separate consideration of each individual entity beforehand being avoided.
During the extractionxe2x80x94according to the inventionxe2x80x94of the parasitic capacitances on the basis of the variant classification, a network list is generated whose size remains manageable. Such a network list can be analyzed very efficiently using hierarchical analysis methods. After the cell entities have been classified, every entity of a cell is not considered individually by means of the parasitics extraction, rather the generated variants of the cell entities are accessed. As a result, the performance of the extraction is considerably increased.
The data structure which is generated by the variant formation according to the invention is constructed fully hierarchically, the cell entities being classified on the basis of the network classification. The electrical properties of the parasitic capacitances are advantageously used, rather than a geometrical quantity, for the cell variant classification according to the invention.
According to one embodiment of the invention, the invention""s step of classifying the cell entities of each cell into different variants for all of the networks by using the differential capacitance values as a basis is performed as follows.
In general, the tolerated deviation can be specified in absolute terms in femtofarads or in relative terms in percent. The exemplary embodiment uses exclusively the absolute deviation.
Tolerance values T1 and T2 and a value for a running variable k are defined at the beginning. In this case, T1 is an absolute tolerance value with the unit in capacitance, and T2 is a relative tolerance value in percent.
A cell from the previously generated network list, a network from said cell and also a k-th cell entity of said cell are subsequently selected.
In a next method step, the differential capacitance value Dk is determined for the k-th cell entity from the difference in the sum of the intrinsic and lateral capacitance values for the selected network and from the sum of the intrinsic and lateral capacitance values of the k-th cell entity.
In the next method step according to the invention, a check is made to determine whether a variant V exists for which the following holds true:
|Dkxe2x88x92Dv|xe2x89xa6T1 and (|Dkxe2x88x92Dv|)/Dv* 100xe2x89xa6T2
If this is not the case, in the next step a new variant V having the value Dv=Dk is generated, and in the next step after that the k-th cell entity of the cell is classified into the variant V.
If a variant exists for which the above conditions are met, then in the next step the k-th cell entity of the cell is classified into said variant V.
Afterward, the running variable k is incremented by a predeterminable value, in particular by the value 1.
In the next method step according to the invention, a check is made to determine whether a k-th cell entity exists.
If a k-th cell entity of the cell exists, the method steps are repeated starting from the selection of the k-th cell entity of the cell.
If a k-th cell entity of the cell does not exist, in a next method step a test is effected to determine whether a further network exists in the cell considered.
If this is the case, this network is selected and a value for a running variable k is defined. The method steps are repeated starting from the step of selecting the k-th cell entity of the cell.
By virtue of this embodiment of the invention, cell entities are classified into different variants rapidly and reliably on the basis of their environment-dependent capacitive properties.
Using the tolerance values T1 and T2, which can be individually prescribed by a user, it is possible to set the degree of similarity of the cell entities combined in the same variant V in each case and also the total number of variants in a user-defined manner.
A differential capacitance value Dk is accessed transparently in order to classify the cell entities into the individual variants.
The following method steps according to the invention can advantageously be repeated for further or for all cells of the network list:
definition of up to two tolerance values T1 and T2 and a value for a running variable k,
selection of a cell from the network list,
selection of a network of the selected cell,
selection of the k-th cell entity of the cell,
determination of the differential capacitance value Dk for the k-th cell entity from the difference in the sum of the intrinsic and lateral capacitance values for the selected network and from the sum of the intrinsic and lateral capacitance values of the k-th cell entity,
testing whether a variant V exists for which
|Dkxe2x88x92Dv|xe2x89xa6T1 and (|Dkxe2x88x92Dv|)/Dv*100xe2x89xa6T2,
if yes: continuation with the step after the next step,
formation of a new variant V with Dv=Dk,
classification of the k-th cell entity of the cell into said variant V,
incrementing of k by a predeterminable value,
testing whether a k-th cell entity of the cell exists, if yes: continuation with the step of selection of a network of the selected cell,
testing whether a further network exists in the cell considered, if yes: selection of this network, definition of a value for the running variable k, continuation with the step of selection of a network of the selected cell.
The execution of the method steps according to the invention results in a complete classification of the network list into variants of environment-dependent cell entities.
In the above-outlined further embodiment of the invention, the following method steps:
testing whether a variant V exists for which
|Dkxe2x88x92Dv|xe2x89xa6T1 and (|Dkxe2x88x92Dv|)/Dv*100xe2x89xa6T2,
if yes: continuation with the step after the next step,
formation of a new variant V with Dv=Dk,
classification of the k-th cell entity of the cell into said variant V,
are replaced, starting from the second network considered, with the following steps:
testing whether a variant V exists for which
|Dkxe2x88x92Dv|xe2x89xa6T1 and (|Dkxe2x88x92Dv|)/Dv*100xe2x89xa6T2 holds true,
if not: continuation with the step after the next step,
testing whether the k-th cell entity and the cell entities already contained in said variant V have previously been classified in different variants, i.e. before the consideration of this network of the cell,
if not: continuation with the step after the next step,
formation of a new variant V with Dv=Dk,
classification of the k-th cell entity of the cell into said variant V.
This ensures that the cell entities are classified into variants particularly reliably and in a manner which also includes the previous results.
With the above and other objects in view there is also provided, in accordance with the invention, a computer program product, comprising a sequence of computer-executable program steps for executing the above-outlined method for simulating an electrical circuit. Similarly, there is also provided, a computer-readable medium, comprising a carrier having computer-executable instructions stored thereon for performing the method for simulating an electrical circuit.
In accordance with an added feature of the invention, the computer-readable medium is a computer storage medium, such as a computer memory, a direct access memory, and/or an electrical carrier signal.
Finally, with the above and other objects in view there is also provided, in accordance with the invention, a simulation method, which comprises downloading a computer program product as outlined above from an electronic data network, such as the Internet, onto a computer connected to the data network, and running the computer program.
That is, the invention is advantageously realized in a computer program for the execution of a method for the simulation of an electrical circuit.
In this case, the computer program is designed in such a way that, after the inputting of a layout of an electrical circuit, a method according to the invention in an embodiment described above can be performed. In this case, as a result of the method, an advantageous simulation of the electrical circuit is possible which accesses variants of cell entities with similar environment-dependent capacitive properties in each case.
A parasitics extraction and a simulation of an electrical circuit can advantageously be performed by means of the method realized on the computer system. The computer program improved according to the invention yields a simple and effective classification of similar cell entities, improved usability of the method for a multiplicity of electrical circuits and a run time improvement compared with the known methods for the simulation of an electrical circuit.
The invention additionally relates to a computer program which is contained on a storage medium, which is stored in a computer memory, which is contained in a direct access memory or which is transmitted on an electrical carrier signal.
Furthermore, the invention relates to a data carrier with such a computer program and also to a method in which such a computer program is downloaded from an electrical data network, such as, for example, from the Internet, onto a computer connected to the data network.
The classification of the variants and the cell entities contained in the respective variants can be output in the form of a xe2x80x9cvariant classification filexe2x80x9d. A subsequent simulation of the electrical circuit builds on this xe2x80x9cvariant classification filexe2x80x9d. The requisite procedure is known to the person skilled in the art and need not be explained here.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the simulation of an electrical circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.